Structures and methods for enhancing capacitors in integrated circuits

ABSTRACT

Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.09/598,355 filed Jun. 21, 2000, which application is incorporated hereinby reference.

TECHNICAL FIELD

The technical field relates generally to semiconductor integratedcircuits. More particularly, it pertains to capacitors in semiconductorintegrated circuits.

BACKGROUND

A capacitor is composed of two layers of a material that is electricallyconductive (hereinafter, electrode) brought near to one another andseparated by a material that is electrically nonconductive. Suppose thecapacitor is connected to a battery with a certain voltage level(hereinafter, energy level). Charges will flow from the battery to bestored in the capacitor until the capacitor exhibits the energy level ofthe battery. Then, suppose further that the capacitor is disconnectedfrom the battery. The capacitor will indefinitely exhibit the energylevel of the battery until the charges stored in the capacitor areremoved either by design or by accident.

This ability of the capacitor to “remember” an energy level is valuableto the operation of semiconductor integrated circuits. Often, theoperation of such circuits may require that data be stored and retrievedas desired. Because of its ability to remember, the capacitor is a majorcomponent of a semiconductor memory cell. One memory cell may store onebit of data. A system of memory cells is a semiconductor memory arraywhere information can be randomly stored or retrieved from each memorycell. Such a system is also known as a random-access memory.

One type of random-access memory is dynamic random-access memory (DRAM).The charges stored in DRAM tend to leak away over a short time. It isthus necessary to periodically refresh the charges stored in the DRAM bythe use of additional circuitry. Even with the refresh burden, DRAM is apopular type of memory because it can occupy a very small space on asemiconductor surface. This is desirable because of the need to maximizestorage capacity on the limited surface area of an integrated circuit

One type of capacitor that supports an increase in storage capacity usesa metal substance as a bottom electrode and an electricallynonconductive material that has a high dielectric constant. The metalsubstance tends to create undesired atomic diffusion in an environmentwith a high temperature. Such a high temperature, however, is needed tofurther process the electrically nonconductive material. The undesiredatomic diffusion may act to degrade the electrically nonconductivematerial. That act compromises the ability of the capacitor to maintainthe charges. This is detrimental to the storage ability of the capacitorand would render such a memory cell defective.

Thus, what is needed are systems, devices, structures, and methods toinhibit the described effect so as to enhance capacitors with a highdielectric constant in manufacturing environments exhibiting hightemperatures.

SUMMARY

The above-mentioned problems with capacitors as well as other problemsare addressed by the present invention and will be understood by readingand studying the following specification. Systems, devices, structures,and methods are described which accord these benefits.

An illustrative embodiment includes a capacitor. The capacitor includesa first electrode, a dielectric having a first compound, and a secondelectrode having a second compound that includes a third and a fourthsubstance. The first compound of the dielectric includes a firstsubstance and a second substance. The first compound includes ditantalumpentaoxide. The second electrode also contains a trace amount of thethird substance. The second compound in an as-deposited state includes asubstantial amount of the fourth substance. The trace amount of thethird substance is oxidized during the crystallization of the dielectricsuch that a diffusion of at least one of the first substance and thesecond substance is inhibited. The crystalline structure of thedielectric describes substantially a (001) lattice plane. The secondcompound includes RuO_(x). The x is indicative of a desired number ofatoms.

Another illustrative embodiment includes a method for enhancing asemiconductor structure that stores charges. The method includes forminga conductive layer of RuO_(x), crystallizing to form RuO₂ and a traceamount of Ru, forming an amorphous insulator layer of Ta₂O₅, and forminga crystallized Ta₂O₅ with a desired lattice plane such that thepermittivity of the crystallized Ta₂O₅ is greater than about 25.

These and other embodiments, aspects, advantages, and features of thepresent invention will be set forth in part in the description whichfollows, and in part will become apparent to those skilled in the art byreference to the following description of the invention and referenceddrawings or by practice of the invention. The aspects, advantages, andfeatures of the invention are realized and attained by means of theinstrumentalities, procedures, and combinations particularly pointed outin the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor structure accordingto one embodiment of the present invention.

FIG. 2 is an elevation view of a semiconductor memory array according toone embodiment of the present invention.

FIGS. 3A-3K are cross-sectional views of a semiconductor structureduring processing according to one embodiment of the present invention.

FIG. 4 is a block diagram of a device according to one embodiment of thepresent invention.

FIG. 5 is an elevation view of a semiconductor wafer according to oneembodiment of the present invention.

FIG. 6 is a block diagram of a circuit module according to oneembodiment of the present invention.

FIG. 7 is a block diagram of a memory module according to one embodimentof the present invention.

FIG. 8 is a block diagram of a system according to one embodiment of thepresent invention.

FIG. 9 is a block diagram of a system according to one embodiment of thepresent invention.

FIG. 10 is a block diagram of a system according to one embodiment ofthe present invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention.

The terms wafer and substrate used in the following description includeany base semiconductor structure. Both are to be understood as includingsilicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI)technology, thin film transistor (TFT) technology, doped and undopedsemiconductors, epitaxial layers of silicon supported by a basesemiconductor structure, as well as other semiconductor structures wellknown to one skilled in the art. Furthermore, when reference is made toa wafer or substrate in the following description, previous processsteps may have been utilized to form regions/junctions in the basesemiconductor structure and layer formed above, and the terms wafer orsubstrate include the underlying layers containing suchregions/junctions and any layer that may have been formed above. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims.

FIG. 1 is a cross-sectional view of a semiconductor structure accordingto one embodiment of the present invention. The semiconductor structure100 may illustrate an example of a single DRAM cell. The semiconductorstructure 100 includes a substrate 102, field isolators 104, transistor134, insulation layers 120, another semiconductor structure such as acapacitor 136, and a metallization layer 140. In one embodiment, themetallization layer 140 may be considered a conductive plug. In anotherembodiment, the conductive plug includes polysilicon. The transistor 134includes source/drain regions 106 ₀ and 106 ₁, silicide region 108,spacers 112, gate oxide 114, and gate 116. The source/drain regions 106₀ and 106 ₁ include lightly doped source/drain regions 110. Thecapacitor 136 includes an electrode 124, a dielectric layer 126, andanother electrode 128. The dielectric layer 126 is coupled to theelectrodes 124 and 128.

Charges can be transferred into or removed from the capacitor 136 byturning on the transistor 134. The transistor 134 is turned on by anappropriate voltage level and polarity placed at the gate 116 so that adepletion region and conducting channel are formed between thesource/drain regions 106 ₀ and 106 ₁. If charges are to be transferredinto the capacitor 136, these charges are introduced at the source/drainregion 106 ₀ by a buried bit line 141, so that they may travel acrossthe conducting channel into the source/drain region 106 ₁, conductthrough the metallization layer 140, and enter the electrode 124. Thecharges cannot go any further because the dielectric layer 126 iselectrically nonconductive. However, these charges will attract oppositepolarity charges to appear at electrode 128. Hence, an electric field isset up between the electrodes 124 and 128. Energy is stored in thiselectric field. This electric field is the phenomenon that allows thecapacitor to “remember.”

There exists an industry-wide drive to smaller memory cells to increasestorage density on the limited surface area of an integrated circuit.This has motivated the use of a thin film nonconductive material for useas a dielectric 126 of the capacitor 136. High temperatures may be usedin the processing of the semiconductor structure 100. Such hightemperatures may cause the bottom electrode 124 to undesirably act witha portion of the semiconductor structure 100, such as the dielectric 126of the capacitor 136. Such action may degrade the properties of thedielectric 126 to cause the capacitor 136 to become defective over time.

One example of the degradation of the dielectric 126 includes the use ofa metal substance for the bottom electrode 124. A high temperature(about 750 degrees Celsius or greater) is used to crystallize thedielectric 126. At such a high temperature, thermal vibration in thecrystal structure of the metal substance increases, thereby increasingthe likelihood of structural disruption. Such a structural disruptionintroduces point defects, such as vacancies in the crystal structure ofthe metal substance. Suppose that the dielectric 126 includes a compoundcomprising another metal substance and nonmetal atoms. Under theenvironment as described above, nonmetal atoms of the dielectric 126 maydiffuse to fill the point defects in the crystal structure of the metalsubstance of the bottom electrode 124. Such a diffusion mayshort-circuit the capacitor 136. This may occur because the metalsubstance of the dielectric 126 in the absence of the nonmetal atoms mayconductively couple the electrode 124 to the electrode 128.

One solution includes using lower temperatures (750 degrees Celsius orlower) to crystallize the dielectric 126. However, at such temperatures,the dielectric 126 tends to exhibit high leakage values. This may beattributed to insufficient incorporation of the nonmetal atoms with themetal atoms in the crystal structure of the dielectric 126 at lowtemperatures. Thus, this solution is inadequate.

The embodiments of the present invention solve the above-discussedproblem while enhancing the dielectric 126. In one embodiment, asemiconductor structure for storing charges includes an insulator layerhaving a first compound that includes substances, and a conductive layerhaving a second compound that includes a first substance and a secondsubstance. The second compound in an as-deposited state includes asubstantial amount of the second substance so as to inhibit undesireddiffusion of at least one substance of the first compound from theinsulator layer.

In another embodiment, the semiconductor structure includes an insulatorlayer and a conductive layer having a compound formed from a firstsubstance and a second substance; the conductive layer includes a traceamount of the first substance. The morphology of the semiconductorstructure remains stable when the trace amount of the first substance isoxidized during crystallization of the insulator layer.

In another embodiment, the semiconductor structure includes an insulatorlayer having a permittivity value greater than about 25, and aconductive layer having a compound. The compound remains stable when theinsulator layer is crystallized at a high temperature so as to decreasethe charge leakage of the insulator layer. In one embodiment, theinsulator layer passivates the conductive layer from undesiredoxidation.

In another embodiment, the semiconductor structure includes an insulatorlayer having a permittivity value, and a conductive layer abuttinglycoupled to the insulator layer. The crystalline structure of theinsulator layer describes a desired lattice plane such that thepermittivity value of the insulator layer is greater than about 25. Thedesired lattice plane includes substantially a (001) plane. In anotherembodiment, the desired lattice plane is described by three axes; thedesired plane is parallel to two of the three axes and intersects one ofthe three axes.

In another embodiment, the capacitor 136 includes a first electrode, adielectric that includes ditantalum pentaoxide, and a second electrodehaving a compound that includes a first substance and a secondsubstance. The compound in an as-deposited state includes a substantialamount of the second substance so as to inhibit undesired diffusion at ahigh temperature. The compound includes ruthenium oxide (RuO_(x)). The xis indicative of a desired number of atoms.

In another embodiment, the capacitor 136 includes a first electrode, adielectric that includes ditantalum pentaoxide, and a second electrodehaving a compound that includes a first substance and a secondsubstance. The second electrode includes a trace amount of the firstsubstance. The morphology of the semiconductor structure remains stablewhen the trace amount of the first substance is oxidized duringcrystallization of the dielectric. The compound includes RuOx. The x isindicative of a desired number of atoms.

In another embodiment, the capacitor 136 includes a first electrode, adielectric that includes ditantalum pentaoxide, and a second electrodehaving a compound. The crystalline structure of the dielectric describesa (001) lattice plane. The compound includes RuOx. The x is indicativeof a desired number of atoms.

In another embodiment, the capacitor 136 includes a first electrode, adielectric having a first compound that includes a first substance and asecond substance, and a second electrode having a second compound thatincludes a third and a fourth substance. The first compound includesditantalum pentaoxide. The second electrode includes a trace amount ofthe third substance. The second compound in an as-deposited stateincludes a substantial amount of the fourth substance. The trace amountof the third substance is oxidized during the crystallization of thedielectric such that a diffusion of at least one of the first substanceand the second substance is inhibited. The crystalline structure of thedielectric describes substantially a (001) lattice plane. The compoundincludes RuOx. The x is indicative of a desired number of atoms.

In another embodiment, the capacitor 136 includes a first electrode, adielectric having a first compound that includes a first substance and asecond substance, and a second electrode having a second compound thatincludes a third substance and a fourth substance. The first electrodehas a substance that is selected from a group consisting of TiN, TiON,WN_(x), TaN, Ta, Pt, Pt—Rh, Pt—RhO_(x), Ru, RuO_(x), Ir, IrO_(x), Pt—Ru,Pt—RuO_(x), Pt—Ir, Pt—IrO_(x), SrRuO₃, Au, Pd, Al, Mo, Ag, and Poly-Si.The first compound includes ditantalum pentaoxide. The second electrodeincludes a trace amount of the third substance. The second compound inan as-deposited state includes a substantial amount of the fourthsubstance. The trace amount of the third substance is oxidized duringthe crystallization of the dielectric such that a diffusion of at leastone of the first substance and the second substance is inhibited. Thecrystalline structure of the dielectric describes substantially a (001)lattice plane. The second compound includes RuO_(x), wherein the x isindicative of a desired number of atoms.

FIG. 2 is an elevation view of a semiconductor memory array according toone embodiment of the present invention. The memory array 200 includesmemory cell regions 242 formed overlying active areas 250. Active areas250 are separated by field isolation regions 252. Active areas 250 andfield isolation regions 252 are formed overlying a semiconductorsubstrate.

The memory cell regions 242 are arrayed substantially in rows andcolumns. Shown in FIG. 2 are portions of three rows 201A, 201B and 201C.Separate digit lines (not shown) would be formed overlying each row 201and coupled to active areas 250 through digit line contact regions 248.Word line regions 244 and 246 are further coupled to active areas 250,with word line regions 244 coupled to active areas 250 in row 201B andword line regions 246 coupled to active areas 250 in rows 201A and 201C.The word line regions 244 and 246, coupled to memory cells in thisalternating fashion, generally define the columns of the memory array.This folded bit-line architecture is well known in the art forpermitting higher densification of memory cell regions 242.

FIGS. 3A-3K are cross-sectional views of a semiconductor structureduring processing according to one embodiment of the present invention.FIGS. 3A-3K are cross-sectional views taken along line A-AN of FIG. 2during various processing stages.

Semiconductor structure 300 includes a substrate 302. The substrate 302may be a silicon substrate, such as a p-type silicon substrate. Fieldisolators 304 are formed over field isolation regions 352 of thesubstrate 302. Field isolators 304 are generally formed of an insulatormaterial, such as silicon oxides, silicon nitrides, or siliconoxynitrides. In this embodiment, field isolators 304 are formed ofsilicon dioxide such as by conventional local oxidation of silicon whichcreates substantially planar regions of oxide on the substrate surface.Active area 350 is an area not covered by the field isolators 304 on thesubstrate 302. The creation of the field isolators 304 is preceded orfollowed by the formation of a gate dielectric layer 314. In thisembodiment, gate dielectric layer 314 is a thermally grown silicondioxide, but other insulator materials may be used as described herein.

The creation of the field isolators 304 and gate dielectric layer 314 isfollowed by the formation of a conductively doped gate layer 316,silicide layer 308, and gate spacers 312. These layers and spacers areformed by methods well known in the art. The foregoing layers arepatterned to form word lines in word line regions 344 and 346. A portionof these word lines is illustratively represented by gates 338 ₀, 338 ₁,338 ₂, and 338 ₃. In one embodiment, the silicide layer 308 includes arefractory metal layer over the conductively doped gate layer 316, suchas a polysilicon layer.

Source/drain regions 306 are formed on the substrate 302 such as byconductive doping of the substrate. Source/drain regions 306 have aconductivity opposite the substrate 302. For a p-type substrate,source/drain regions 306 would have an n-type conductivity. Thesource/drain regions 306 include lightly doped source/drain regions 310that are formed by implanting a low-dose substance, such as an n-type orp-type material. Such lightly doped source/drain regions 310 help toreduce high field in the source/drain junctions of a small-geometrysemiconductor structure, such as semiconductor structure 300. In oneembodiment, each of the gates 338 ₀, 338 ₁, 338 ₂, and 338 ₃ is enclosedby a nitride compound layer. The nitride compound layer includes amolecular formula of Si_(x)N_(y). The variables x and y are indicativeof a desired number of atoms. The portion of the word lines that areillustratively represented by gates 338 ₀, 338 ₁, 338 ₂, and 338 ₃ isadapted to be coupled to periphery contacts (not shown). The peripherycontacts are located at the end of a memory array and are adapted forelectrical communication with external circuitry.

The foregoing discussion is illustrative of one example of a portion ofa fabrication process to be used in conjunction with the variousembodiments of the invention. Other methods of fabrication are alsofeasible and perhaps equally viable. For clarity purposes, many of thereference numbers are eliminated from subsequent drawings so as to focuson the portion of interest of the semiconductor structure 300.

FIG. 3B shows the semiconductor structure following the next sequence ofprocessing. A thick insulation layer 320 is deposited overlyingsubstrate 302 as well as field isolation regions 352 and active regions350. Insulation layer 320 is an insulator material such as siliconoxide, silicon nitride, and silicon oxynitride. In one embodiment,insulation layer 320 is a doped insulator material such asborophosphosilicate glass (BPSG), a boron and phosphorous-doped siliconoxide. The insulation layer 320 is planarized, such as bychemical-mechanical planarization (CMP), in order to provide a uniformheight.

FIG. 3C shows the semiconductor structure following the next sequence ofprocessing. The first inhibiting layer 330 ₀ is optionally formed on orabutting the insulation layer 320. The first inhibiting layer 330 ₀includes a nitride compound. In one embodiment, the first inhibitinglayer 330 ₀ includes a metal nitride compound. The nitride compoundincludes a substance with a molecular formula of Si_(x)N_(y). Thevariables x and y are indicative of the desired number of atoms.

The first inhibiting layer 330 ₀ may be formed by any method, such ascollimated sputtering, chemical vapor deposition (CVD), or otherdeposition techniques. In this embodiment, the first inhibiting layer330 ₀ is patterned to form the first inhibiting layer of a semiconductorstructure of interest, such as a capacitor.

FIG. 3D shows the semiconductor structure following the next sequence ofprocessing. The semiconductor structure 300 is patterned usingphotolithography with appropriately placed masks to define futurelocations of memory cells. Then portions of the first inhibiting layer330 ₀ and the insulation layer 320 are exposed and removed along withthe masks. These portions of the first inhibiting layer 330 ₀ and theinsulation layer 320 may be removed by etching or other suitable removaltechniques known in the art. Removal techniques are generally dependenton the material of construction of the layer to be removed as well asthe surrounding layers to be retained. Patterning of the firstinhibiting layer 330 ₀ and the insulation layer 320 creates openingshaving bottom portions exposed to portions of the silicide region 308and sidewalls defined by the insulation layer 320. A metallization layer340 is formed on the silicide region 308 using a suitable depositiontechnique. In one embodiment, the metallization layer 340 may beconsidered a conductive plug. In another embodiment, the conductive plugincludes conductive polysilicon.

FIG. 3E shows the semiconductor structure following the next sequence ofprocessing. A second inhibiting layer 330 ₁ is optionally formed on thefirst inhibiting layer 330 ₀, the insulation layer 320, and themetallization layer 340. The second inhibiting layer 330 ₁ includes anitride compound. In one embodiment, the second inhibiting layer 330,includes a metal nitride compound. The nitride compound includes asubstance with a molecular formula of Si_(x)N_(y). The variables x and yare indicative of the desired number of atoms. The second inhibitinglayer 330 ₁ may be formed by any method, such as collimated sputtering,chemical vapor deposition (CVD), or other deposition techniques.

FIG. 3F shows the semiconductor structure following the next sequence ofprocessing. In one embodiment, the second inhibiting layer 330 ₁ isetched to define a chamber with an aperture that adjoins themetallization layer 340 and two sidewalls extending outwardly from theaperture. In one embodiment, the etching technique is selected from agroup consisting of a spacer etching technique and an etch-backtechnique.

FIG. 3G shows the semiconductor structure following the next sequence ofprocessing. A conductive layer 324 is formed on or adjoining to theinhibiting layer 330 ₀, the insulation layer 320 and the metallizationlayer 340. The conductive layer 324 includes a conductive material. Inone embodiment, the conductive material includes an as-deposited film ofa conductive compound. The conductive compound includes a firstsubstance and a substantial amount of a second substance. The firstsubstance includes ruthenium. The second substance includes oxygen. Theconductive compound includes RuO_(x). The x is indicative of a desirednumber of atoms.

The conductive layer 324 may be formed by any method, such as collimatedsputtering, chemical vapor deposition (CVD), or other depositiontechniques. In this embodiment, the conductive layer 324 forms thebottom conductive layer, or bottom electrode, or bottom plate of asemiconductor structure of interest, such as a capacitor.

In one embodiment, the conductive layer 324 is formed in about 210degrees Celsius. In another embodiment, the first substance includesabout 200 sccm of Ru-HEC. In another embodiment, the second substanceincludes about 250 sccm Of O₂. In another embodiment, the conductivelayer 324 is formed in about 2.5 torrs.

After the formation of the conductive layer 324, in one embodiment, theconductive layer 324 undergoes an act of crystallizing to form acrystallized film. In one embodiment, the act of crystallizing occurs ata temperature that is greater than about 750 degrees Celsius and lessthan about 800 degrees Celsius. In another embodiment, the act ofcrystallizing occurs in an ambient of nitrogen. In another embodiment,the act of crystallizing results in compounds and substances thatinclude ruthenium dioxide and a trace amount of ruthenium.

The conductive layer 324 may undergo a localizing or a polishing processsuch as by a chemical mechanical planarization technique or othersuitable techniques. Such a localizing technique disposes the conductivelayer 324 to adjoin the metallization layer 340. In another embodiment,the conductive layer 324 undergoes an etching process such as by a wetetch technique or a dry etch technique. The result is as shown in FIG.3G.

FIG. 3H shows the semiconductor structure following the next sequence ofprocessing. An insulator layer (or dielectric layer) 326 is formed on oradjoining the first inhibiting layer 330 ₀, the second inhibiting layer330 ₁, and the conductive layer 324. The dielectric layer 326 includesan oxide compound. In one embodiment, the dielectric layer 326 is a thinfilm dielectric. In one embodiment, the oxide compound includesditantalum pentaoxide. In another embodiment, the dielectric layer 326includes a thin film of a high permittivity insulator material. Inanother embodiment, the dielectric layer 326 includes an amorphousinsulator layer. The dielectric layer 326 may be formed by any method,such as collimated sputtering, chemical vapor deposition (CVD), or otherdeposition techniques.

After the formation of the dielectric layer 326, in one embodiment, thedielectric layer 326 undergoes an act of crystallizing to formcrystallized Ta₂O₅. The act of crystallizing to form crystallized Ta₂O₅converts a trace amount of ruthenium that may remain from the formationof the conductive layer 324. Such conversion includes converting thetrace amount of ruthenium into ruthenium dioxide. In one embodiment, theact of crystallizing occurs at a temperature of about 800 degreesCelsius. In another embodiment, the act of crystallizing occurs in anambient of dinitrogen oxide. In another embodiment, the act ofcrystallizing occurs in an ambient of oxygen.

In one embodiment, the act of crystallizing forms a crystallized Ta₂O₅with a desired lattice plane such that the permittivity of thecrystallized Ta₂O₅ is greater than about 25. The desired lattice planeincludes substantially a (001) lattice plane.

FIG. 3I shows the semiconductor structure following the next sequence ofprocessing. A conductive layer 328 is formed on the dielectric layer326. The conductive layer 328 includes a conductive material. Theconductive layer 328 may be formed by any method, such as collimatedsputtering, chemical vapor deposition (CVD), or other depositiontechniques. In this embodiment, the conductive layer 328 forms the topconductive layer, or top electrode, or top plate of a semiconductorstructure of interest, such as a capacitor.

A third inhibiting layer 330 ₂ is optionally formed on the conductivelayer 328. The third inhibiting layer 330 ₂ includes a nitride compound.In one embodiment, the third inhibiting layer 330 ₂ includes a metalnitride compound. The nitride compound includes a substance with amolecular formula of Si_(x)N_(y). The variables x and y are indicativeof the desired number of atoms. The third inhibiting layer 330 ₂ may beformed by any method, such as collimated sputtering, chemical vapordeposition (CVD), or other deposition techniques.

FIG. 3J shows the semiconductor structure following the next sequence ofprocessing. The semiconductor structure 300 is patterned usingphotolithography with appropriately placed masks to define a number ofcapacitors to be used in memory cells. Then portions of the firstinhibiting layer 330 ₀, the dielectric layer 326, the conductive layer328, and the second inhibiting layer 330 ₂ are exposed and removed alongwith the masks. Those of the first inhibiting layer 330 ₀, thedielectric layer 326, the conductive layer 328, and the secondinhibiting layer 330 ₂ may be removed by etching or other suitableremoval techniques known in the art. Removal techniques are generallydependent on the material of construction of the layer to be removed aswell as the surrounding layers to be retained. Patterning of the firstinhibiting layer 330 ₀, the dielectric layer 326, the conductive layer328, and the second inhibiting layer 330 ₂ defines two edges orterminals for each capacitor 336 ₀ and 336 ₁. These edges are the resultof etching the various portions of the semiconductor structure 300 downto the insulation layer 320.

FIG. 3K shows the semiconductor structure following the next sequence ofprocessing. A fourth inhibiting layer 330 ₃ is optionally formed on theinsulator layer 320 and the capacitors 336 ₀ and 336 ₁. The fourthinhibiting layer 330 ₃ includes a nitride compound. In one embodiment,the fourth inhibiting layer 330 ₃ includes a metal nitride compound. Thenitride compound includes a substance with a molecular formula ofSi_(x)N_(y). The variables x and y are indicative of the desired numberof atoms. The fourth inhibiting layer 330 ₃ may be formed by any method,such as collimated sputtering, chemical vapor deposition (CVD), or otherdeposition techniques. Once the fourth inhibiting layer 330 ₃ is formed,a portion of the fourth inhibiting layer 330 ₃ is removed using asuitable technique, such as reactive ion etching. Such etching definessidewall spacers as shown in FIG. 3J.

A digit line contact 341 is formed over the digit line contact regions348. The formation of the digit line contact 341 and the completion ofthe semiconductor structure 300 do not limit the embodiments of thepresent invention and as such will not be discussed here in detail.

FIG. 4 is a block diagram of a device according to one embodiment of thepresent invention. The memory device 400 includes an array of memorycells 402, address decoder 404, row access circuitry 406, column accesscircuitry 408, control circuitry 410, and input/output circuit 412. Thememory device 400 can be coupled to an external microprocessor 414, ormemory controller for memory accessing. The memory device 400 receivescontrol signals from the processor 414, such as WE*, RAS*, and CAS*signals. The memory device 400 is used to store data which is accessedvia I/O lines. It will be appreciated by those skilled in the art thatadditional circuitry and control signals can be provided, and that thememory device 400 has been simplified to help focus on the invention. Atleast one of the memory cells includes a semiconductor structure inaccordance with the aforementioned embodiments.

It will be understood that the above description of a DRAM (DynamicRandom Access Memory) is intended to provide a general understanding ofthe memory and is not a complete description of all the elements andfeatures of a DRAM. Further, the invention is equally applicable to anysize and type of memory circuit and is not intended to be limited to theDRAM described above. Other alternative types of devices include SRAM(Static Random Access Memory) or Flash memories. Additionally, the DRAMcould be a synchronous DRAM commonly referred to as SGRAM (SynchronousGraphics Random Access Memory), SDRAM (Synchronous Dynamic Random AccessMemory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well asSynchlink or Rambus DRAMs and other emerging memory technologies.

As recognized by those skilled in the art, memory devices of the typedescribed herein are generally fabricated as an integrated circuitcontaining a variety of semiconductor devices. The integrated circuit issupported by a substrate. Integrated circuits are typically repeatedmultiple times on each substrate. The substrate is further processed toseparate the integrated circuits into dies as is well known in the art.

FIG. 5 is an elevation view of a semiconductor wafer according to oneembodiment of the present invention. In one embodiment, a semiconductordie 510 is produced from a wafer 500. A die is an individual pattern,typically rectangular, on a substrate that contains circuitry, orintegrated circuit devices, to perform a specific function. At least oneof the integrated circuit devices includes a memory cell that includes asemiconductor structure as discussed in the various embodimentsheretofore in accordance with the invention. A semiconductor wafer willtypically contain a repeated pattern of such dies containing the samefunctionality. Die 510 may contain circuitry for the inventive memorydevice, as discussed above. Die 510 may further contain additionalcircuitry to extend to such complex devices as a monolithic processorwith multiple functionality. Die 510 is typically packaged in aprotective casing (not shown) with leads extending therefrom (not shown)providing access to the circuitry of the die for unilateral or bilateralcommunication and control.

FIG. 6 is a block diagram of a circuit module according to oneembodiment of the present invention. Two or more dies 610 may becombined, with or without protective casing, into a circuit module 600to enhance or extend the functionality of an individual die 610. Circuitmodule 600 may be a combination of dies 610 representing a variety offunctions, or a combination of dies 610 containing the samefunctionality. One or more dies 610 of circuit module 600 contain atleast one semiconductor structure in accordance with the embodiments ofthe present invention.

Some examples of a circuit module include memory modules, devicedrivers, power modules, communication modems, processor modules, andapplication-specific modules, and may include multilayer, multichipmodules. Circuit module 600 may be a subcomponent of a variety ofelectronic systems, such as a clock, a television, a cell phone, apersonal computer, an automobile, an industrial control system, anaircraft, and others. Circuit module 600 will have a variety of leads612 extending therefrom and coupled to the dies 610 providing unilateralor bilateral communication and control.

FIG. 7 is a block diagram of a memory module according to one embodimentof the present invention. Memory module 700 contains multiple memorydevices 710 contained on support 715, the number depending upon thedesired bus width and the desire for parity. Memory module 700 accepts acommand signal from an external controller (not shown) on a command link720 and provides for data input and data output on data links 730. Thecommand link 720 and data links 730 are connected to leads 740 extendingfrom the support 715. Leads 740 are shown for conceptual purposes andare not limited to the positions as shown. At least one of the memorydevices 710 includes a memory cell that includes a semiconductorstructure as discussed in various embodiments in accordance with theinvention.

FIG. 8 is a block diagram of a system according to one embodiment of thepresent invention. Electronic system 800 contains one or more circuitmodules 802. Electronic system 800 generally contains a user interface804. User interface 804 provides a user of the electronic system 800with some form of control or observation of the results of theelectronic system 800. Some examples of user interface 804 include thekeyboard, pointing device, monitor, or printer of a personal computer;the tuning dial, display, or speakers of a radio; the ignition switch,gauges, or gas pedal of an automobile; and the card reader, keypad,display, or currency dispenser of an automated teller machine. Userinterface 804 may further describe access ports provided to electronicsystem 800. Access ports are used to connect an electronic system to themore tangible user interface components previously exemplified. One ormore of the circuit modules 802 may be a processor providing some formof manipulation, control, or direction of inputs from or outputs to userinterface 804, or of other information either preprogrammed into, orotherwise provided to, electronic system 800. As will be apparent fromthe lists of examples previously given, electronic system 800 will oftencontain certain mechanical components (not shown) in addition to circuitmodules 802 and user interface 804. It will be appreciated that the oneor more circuit modules 802 in electronic system 800 can be replaced bya single integrated circuit. Furthermore, electronic system 800 may be asubcomponent of a larger electronic system. At least one of the circuitmodules 802 includes a memory cell that includes a semiconductorstructure as discussed in various embodiments in accordance with theinvention.

FIG. 9 is a block diagram of a system according to one embodiment of thepresent invention. Memory system 900 contains one or more memory modules902 and a memory controller 912. Each memory module 902 includes atleast one memory device 910. Memory controller 912 provides and controlsa bidirectional interface between memory system 900 and an externalsystem bus 920. Memory system 900 accepts a command signal from theexternal bus 920 and relays it to the one or more memory modules 902 ona command link 930. Memory system 900 provides for data input and dataoutput between the one or more memory modules 902 and external systembus 920 on data links 940. At least one of the memory devices 910includes a memory cell that includes a semiconductor structure asdiscussed in various embodiments in accordance with the invention.

FIG. 10 is a block diagram of a system according to one embodiment ofthe present invention. Computer system 1000 contains a processor 1010and a memory system 1002 housed in a computer unit 1005. Computer system1000 is but one example of an electronic system containing anotherelectronic system, e.g., memory system 1002, as a subcomponent. Thememory system 1002 may include a memory cell that includes asemiconductor structure as discussed in various embodiments of thepresent invention. Computer system 1000 optionally contains userinterface components. These user interface components include a keyboard1020, a pointing device 1030, a monitor 1040, a printer 1050, and a bulkstorage device 1060. It will be appreciated that other components areoften associated with computer system 1000 such as modems, device drivercards, additional storage devices, etc. It will further be appreciatedthat the processor 1010 and memory system 1002 of computer system 1000can be incorporated on a single integrated circuit. Such single-packageprocessing units reduce the communication time between the processor andthe memory circuit.

CONCLUSION

Systems, devices, structures, and methods have been described to addresssituations where, at high temperature, undesired diffusion acts againsta high permittivity dielectric in a capacitor such that degradationoccurs. Capacitors that are formed using at least one technique asdescribed heretofore benefit from the dual ability of having an increasein storage capability yet maintain reliability in the process ofmanufacturing involving high temperatures.

Although the specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. It is to be understood that the above description is intendedto be illustrative, and not restrictive. Combinations of the aboveembodiments and other embodiments will be apparent to those of skill inthe art upon reviewing the above description. The scope of the inventionincludes any other applications in which the above structures andfabrication methods are used. Accordingly, the scope of the inventionshould only be determined with reference to the appended claims, alongwith the full scope of equivalents to which such claims are entitled.

1. A semiconductor structure comprising: a metallization layer; a firstconductive layer directly contacting the metallization layer, theconductive layer including a first compound, the first compoundincluding a first substance and a second substance; an insulator layerformed directly on the first conductive layer, the insulator layerincluding a second compound; and a second conductive layer formeddirectly on the insulator layer.
 2. The semiconductor structure of claim1, wherein the first conductive layer further includes the firstsubstance separated from the first compound of the first substance andthe second substance.
 3. The semiconductor structure of claim 1, whereinthe first compound includes ruthenium and oxygen.
 4. The semiconductorstructure of claim 3, wherein the second compound includes tantalum andoxygen.
 5. The semiconductor structure of claim 4, wherein themetallization layer includes polysilicon.
 6. The semiconductor structureof claim 4, wherein the first conductive layer further includesruthenium separated from the first compound of ruthenium and oxygen. 7.The semiconductor structure of claim 1, wherein the first compoundincludes a substantial amount of the second substance for inhibitingdiffusion of the second compound from the insulator layer.
 8. Thesemiconductor structure of claim 1, wherein the second conductive layerincludes a conductive portion formed below a surface of the firstconductive layer.
 9. A semiconductor structure comprising: ametallization layer directly contacting a substrate; a first conductivelayer directly contacting the metallization layer, the conductive layerincluding a first compound, the first compound including a metalsubstance and a nonmetal substance; an insulator layer formed directlyon the first conductive layer, the insulator layer including a secondcompound, the second compound including a metal substance and a nonmetalsubstance; and a second conductive layer formed directly on theinsulator layer.
 10. The semiconductor structure of claim 9, wherein themetal substance of the first compound includes ruthenium.
 11. Thesemiconductor structure of claim 10, wherein the metal substance of thesecond compound includes tantalum.
 12. The semiconductor structure ofclaim 11, wherein the nonmetal substance of the first compound includesoxygen.
 13. The semiconductor structure of claim 12, wherein thenonmetal substance of the second compound includes oxygen.
 14. Thesemiconductor structure of claim 13, wherein the first compound includesa substantial amount of the oxygen for inhibiting diffusion of thesecond compound from the insulator layer.
 15. The semiconductorstructure of claim 14, wherein the second conductive layer includes afirst conductive portion and a second conductive portion uniformlyformed with the first conductive portion, and wherein one of the firstand second conductive portions is surrounded by the first conductivelayer.
 16. A semiconductor structure comprising: a transistor; and acapacitor coupled to the transistor via a region of a substrate, thecapacitor including: a capacitor plug coupled to the region of thesubstrate; a first capacitor electrode directly contacting the capacitorplug, the first capacitor electrode including a first compound, thefirst compound including a first substance and a second substance; acapacitor dielectric layer formed directly on the first capacitorelectrode, the capacitor dielectric including a second compound; and asecond capacitor electrode formed directly on the capacitor dielectric.17. The semiconductor structure of claim 16, wherein the first compoundincludes ruthenium and oxygen.
 18. The semiconductor structure of claim17, wherein the second compound includes tantalum and oxygen.
 19. Thesemiconductor structure of claim 16, wherein the capacitor plug is abovea surface of the substrate.
 20. The semiconductor structure of claim 16,wherein the transistor includes a first source/drain region formed inthe substrate, a second source/drain region formed in the substrate, anda gate formed above the substrate for controlling the transistor fortransferring a charge between the capacitor and one of the first andsecond source/drain regions.
 21. The semiconductor structure of claim20, wherein the second capacitor electrode includes a first conductiveportion and a second conductive portion uniformly formed with the firstconductive portion, and wherein one of the first and second conductiveportions is surrounded by the first capacitor electrode.
 22. A systemcomprising: a processor; and a dynamic random access memory devicecoupled to the processor, the dynamic random access memory deviceincluding a plurality of memory cells, at least one of the memory cellsincluding: a transistor; and a capacitor coupled to the transistor via aregion of a substrate, the capacitor including: a capacitor plug coupledto the region of the substrate; a first capacitor electrode directlycontacting the capacitor plug, the first capacitor electrode including afirst compound, the first compound including a first substance and asecond substance; a capacitor dielectric layer formed directly on thefirst capacitor electrode, the capacitor dielectric including a secondcompound; and a second capacitor electrode formed directly on thecapacitor dielectric.
 23. The system of claim 22, wherein the firstcompound includes RuOx, wherein x is a number of atoms.
 24. The systemof claim 23, wherein the second compound includes ditantalum pentaoxide.25. The system of claim 24, wherein the transistor includes a firstsource/drain region formed in the substrate, a second source/drainregion formed in the substrate, and a gate formed above the substratefor controlling the transistor for transferring a charge between thecapacitor and a bit line of the memory device via the first and secondsource/drain regions.
 26. The system of claim 25, wherein the capacitorplug is above a surface of the substrate.
 27. The system of claim 26,wherein the second capacitor electrode includes a conductive portionformed below a surface of the first capacitor electrode.
 28. A methodcomprising: transferring a charge in a semiconductor structure, thesemiconductor structure including a metallization layer, a firstconductive layer directly contacting the metallization layer, theconductive layer including a first compound, the first compoundincluding a first substance and a second substance, an insulator layerformed directly on the first conductive layer, the insulator layerincluding a second compound, and a second conductive layer formeddirectly on the insulator layer.
 29. The method of claim 28, wherein thefirst conductive layer further includes the first substance separatedfrom the first compound of the first substance and the second substance.30. The method of claim 28, wherein the first compound includesruthenium and oxygen.
 31. The method of claim 30, wherein the secondcompound includes tantalum and oxygen.
 32. The method of claim 31,wherein the first conductive layer further includes ruthenium separatedfrom the first compound of ruthenium and oxygen.